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VNU Journal of Science: Comp. Science & Com. Eng., Vol. 31, No. 2 (2015) 56–65
Design and Modeling of a Voltage-Frequency Controller for Network-on-Chip Routers based on Fuzzy-Logic
Hai-Phong Phan, Xuan-Tu Tran
SIS Laboratory, VNU University of Engineering and Technology, 144 Xuan Thuy road, Cau Giay district, Hanoi, Vietnam
Abstract
Network-on-Chip (NoC) paradigm allows designers to integrate eciently more intellectual properties (IPs) into a single chip system. However, the power consumption has become one of the most critical issues for designing such large complex systems. Low power design can be achieved by scaling the voltage and frequency of the target components. The question is how to make the voltage-frequency scaling adaptable to the required performance of the system at run-time while reducing as much as possible the power consumption. In this paper, we present the design and modeling of a Voltage-Frequency Controller for NoC routers based on fuzzy-logic processing. The communication trac of a network router will be predicted by a fuzzy-logic algorithm. Then the voltage and frequency of the router will be dynamically scaled according to the predicted results in order to get power consumptionoptimalforthenetworkrouter. TheVoltage-FrequencyControlleristhenmodeledatregister-transfer level using VHDL – a hardware description language. The most important part of the proposed controller, the fuzzy-logic processor (FLP) designed with the famous Sugeno model, has been successfully implemented on FPGA devices.
2015 Published by VNU Journal of Sciences.
Manuscript communication: received 20 May 2015, revised 16 June 2015, accepted 25 June 2015. Corresponding author: Hai-Phong Phan, phongph.de12@vnu.edu.vn
Keywords: Low Power, Network-On-Chip, DVFS, Fuzzy Logic.
1. Introduction
The fuzzy set theory was ﬁrst proposed by L.A Zadeh in 1965 [1]. It has been widely applied in many application ﬁelds, from control theory to artiﬁcial intelligence. The typical ﬁelds in which the fuzzy logic theory has been successfully applied include automation control, power saving, data processing, signal processing, especially in robotic design. Many researches
In the medical ﬁeld, fuzzy logic theory has been studied and applied in many dierent subjects, especially in the ﬁeld of biomedical signal processing. In [4], Y. C. Yeh et al. introduced a simple method to study the eectiveness of ECG signals using fuzzy logic theory. Reference [5] also introduced a technique based on fuzzy logic theory to handle the MRI images eectively.
focus on the design of robots with human Previously, fuzzy logic systems are usually
behaviors based on fuzzy logic. By using fuzzy logic algorithms, the behavior of robots can be implemented through the decision “IF–THEN”
implemented by software. The advantages of this method are the ability of quick deployment, easy modiﬁcation, time reduction in development, and
which is similar to human thinking. Therefore, lowcost. However,oneofthemostdisadvantages
robots can have “thinking” and action as humans more than the previous robots generation [2, 3].
is that the processing and computation speed are tooslow. Thisaectstheimplementationoffuzzy
H.P. Phan, X.T. Tran / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 31, No. 2 (2015) 56–65 57
logic in real-time systems. Input_1 Input_2
FZ (IF‐THEN rule) DFZ Fuzzy logic processor
Fuzzy logic theory has prompted the researchers to develop fuzzy logic systems with faster processing and calculating speed, and more power eciency. One of the recent trends for developing fuzzy logic systems is to deploy the system as a hardware core to increase the
Max average
Counter N Counter S
Counter W Counter E
Counter IP Router
Derivative Vdd – Fclk Adjusting
processing speed of the system [6, 7, 8].
Besides, the power consumption is also an important factor in designing complex systems, especially in designing Network-on-Chip (NoC) based systems. The NoC paradigm has been recently known as an emerging solution for designing large, complex system-on-chips (SoCs) [9]. In the NoC based systems, computing units (i.e. Intellectual Properties or IPs) communicates with each other using a micro network that is composed of network routers and network links. Low power techniques for this kind of systems are based on the fact that the system never works at its maximum power capacity. There often exists some idle or low speed operating parts of the system during operating time.
In this paper, we focus on designing a voltage-frequency controller for NoC routers. The role of the proposed controller is to adjust the frequency and voltage of the target router according to its workload (the communication trac going through). Therefore, the power consumption of each router as well as the whole system can be reduced while keeping system performance suitable. To do that, we apply a fuzzy logic algorithm using Sugeno model [10] in the controller. The design is then modeled andimplementedusingVHDLatregister-transfer level.
Fig. 1: The proposed Voltage-Frequency Controller.
2. TheProposedVoltage-FrequencyController
In this paper, we assume that the trac going through a router is also a quantity that reﬂects the activities of this router. If the router has a large communication trac, it must be supplied a higher frequency, as well as a higher voltage, to meet the high data transmission rate and vice versa.
Therefore, we propose to use a voltage-frequency controller to scaling voltage and frequency of the router according to the activities of it in order to reduce the power consumption of a router in a NoC based system. To do that the controller will monitor the trac through the router, then predict the change of trac to make a decision to increase or decrease the values of voltage and frequency accordingly.
To simplify the structure and reduce hardware resources of the system, we propose a Voltage-Frequency Controller (VFC) as shown in Figure 1. In this controller, we use a fuzzy logic processor to predict the communication trac and make decision about the values of frequency and voltage.
In this architecture, each input port of the target router will be equipped with a trac counter. These counters count the data ﬂits
passing through the router in certain clock cycles
The remaining part of the paper is organized as (average trac) based on the corresponding follows. Section 2 presents the proposed Voltage- response signals from the router. Since the router Frequency Controller for NoC routers. The normally has 5 input/output ports [11], there will
modeling of this VFC is discussed in Section 3. Thesimulationandexperimentalresultsaregiven
be5communicationtracvaluesfromtherouter. The maximum trac value passing through the
in Section 4. Finally, conclusions and remarks router is then decided by the Max Average (MA) will be provided in Section 5. block. In fact, the MA will compare and ﬁnd the
58 H.P. Phan, X.T. Tran / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 31, No. 2 (2015) 56–65
maximum value of the ﬁve average trac values given by the router. Finally, this information will be sent to the Input 1 of the FLP for being processed.
The Derivative (DER) block calculates the derivative of tracs obtained from the counters.
resp_in
rst_n
clk
Signal_counter
Clock counter
Counter_X
val_count_out (15:0)
To do that, it receives the trac values from the counters and store these values to buers. The derivation of trac will be calculated by the present value and the previous value. The DER determines the derivative value of trac according to the maximum trac value decided
Fig. 2: The model of Counter x.
clk_count< x”64”
count clk_count + ‘1’ val_count + ‘1’
by MA block and then gives it to Input 2 of the FLP for further processes.
The Fuzzy Logic Processor (FLP) will process the given information (maximum trac value and derivative value) to predict the next
rst_n = ‘0’ init clk_count <= x“00”
val_count <= x”0000”
clk_count= x”64”
count_full val_count <= val_count_out
communication load passing through the router
and decide the suitable voltage and frequency Fig. 3: The ﬁnite state machine of Counter x.
supplied to the router. It is constructed from
the three sub-blocks: the Fuzziﬁcation (FZ), the Fuzzy Engine (FE) and the Defuzziﬁcation (DFZ), as described in Figure 1. As mentioned above, the operation of FLP is based on Sugeno model to simplify the process of modeling and calculation. Asaresult,thisleadstothereduction of hardware resources required for implementing the whole voltage-frequency controller.
TheVoltage-FrequencyAdjusting(VFA)block controlsthevoltageandthefrequencysuppliedto the router. In this design, the router is supplied by three pairs of frequency voltage values (low, medium, high). When the frequency is changed, the voltage will be also adjusted to new level corresponding to the new frequency. The change of frequency is determined by a control signal at the output of FLP.
3. Modeling the Voltage-Frequency Controller
3.1. The Counter
complete). When the Clock counter reach a ﬁxed value, thenumberofeventsinSignal countblock is sent to the output of Counter x as a value of trac.
The activities of Counter x are modeled as a ﬁnite state machine (FSM) with three states: init st, count st and count full st (Figure 3). In the init st state, all of signals will be reset to the initial values. The next state of the init st will be count st state. The count st state will count the events of signal resp in and signal clk. If the number of clk’s events equals 0x64, the next state of FSM is count full st state. In the count full st state, number events of resp in signal will be sent to the output as a value of trac and FSM come back to the init st state. At this state, a signal (end count) is also sent to the DER to warn that a counting process has been ﬁnished.
3.2. The Max Average
The MA block receives trac values from
The model of Counter x is described in the Counter x at ﬁve ports of the router. By
Figure 2. In this model, the Clock counter block is used to count a number of the clock signal -(clk) - events. The Signal counter block counts events from the resp in signal (a handshaking signal at the router indicating a ﬂit transaction
comparing those values, this block will chose the maximum value between them and send it to input 1 of the FLP. Simply, the structure of this block is the combination of 16-bit comparators (COMP) as in Figure 4.
H.P. Phan, X.T. Tran / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 31, No. 2 (2015) 56–65 59
Counter_N
Counter_S
Counter_W
Counter_E Maxtraffic
Counter_IP
MaxAverage
Fig. 6: The operations of a Sugeno model. Fig. 4: The diagram of Max Average block.
traff (15:0) nw_reg
SUB
pr_reg
der_traff (15:0)
3.4. The Fuzzy-Logic Processor
3.4.1. An introduction about Sugeno-type fuzzy inference
ModelSugeno, orTakagi-Sugeno-Kang, isone of methods of fuzzy inference. Introduced in
1985 [10], it is similar to the Mamdani method
Derivative in many respects. The ﬁrst two parts of the
fuzzy inference process, fuzzifying the inputs Fig. 5: The block diagram of the Derivative. and applying the fuzzy operator, are exactly the
same. The main dierence between Mamdani
3.3. The Derivative
The main structure of the DER is composed of two 16-bit registers. One register stores the trac value at present time. The other one stores the value of a frame of time before. The derivative of trac is calculated as an absolute of subtraction between those registers.
The source code of Process describes the DER block as below:
der process : process ( end in , rst n ) is begin
if rst n = ’0’ then
dev traf out <= x”0000” ; reg nx <= x”0000” ;
reg pr <= x”0000” ;
elsif end in ’ event and end in =’1’ then reg pr <= val traf in ;
reg nx <= reg pr ;
if reg pr > reg nx then
dev traf out <= reg pr reg nx ; else
dev traf out <= reg nx reg pr ; end if ;
end if ;
end process der process ;
andSugenoisthattheSugenooutputmembership functions are either linear or constant.
A typical rule in a Sugeno fuzzy model has the form:
If Input 1 = x and Input 2 = y, then Output is z = ax + by + c
For a zero-order Sugeno model, the output level z is a constant (a = b = 0).
A Sugeno rule operates as shown in the diagram depicted in Figure 6.
The fuzziﬁcation converts a clean value of input to a fuzzy value based on the membership functions (MSF). This value is characterized by the degree of MSF - (x) and depends on the shape of MSF, the number of partitions of MSF, and the correlation membership functions.
For calculating the degree of MFS, dierent shapes of membership functions have been already proposed. Trapezoidal, Gaussian, triangular are some of the common shapes for membership functions.
The output level zi of each rule is weighted by the ﬁring strength wi of the rule. For example, for an AND rule with Input 1 = x and Input 2 = y, the ﬁring strength is
wi = ANDRule(1(x);2(y)) (1)
60 H.P. Phan, X.T. Tran / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 31, No. 2 (2015) 56–65
Input MSF_1
Input_1
Input MSF_2 AND Wi
Input_2
Fuzzification
Zi=ax+by+c
Fuzzy Engine
Zout
Zi
Defuzzification
Fig. 7: Fuzzy-logic processor (FLP) model.
Input_1
Input_2
Process()
Cal. degree of traff_msf
Process()
Cal. degree of dev_traff_msf
RankInput
AND
Process()
Cal. output of rule(i)
Wi
Center Gravity
Zi
Zout
Fig. 8: Processing diagam of the fuzzy-logic processor.
The ﬁnal output of the system is the weighted average of all rule outputs, computed as
P wi:zi
Final Output = i=1 (2)
wi i=1
where N is the number of rules.
3.4.2. Modeling the Fuzzy-Logic Processor
The proposed Fuzzy-Logic Processor (FLP)
is a fuzzy logic system with two inputs and
calculation of the ﬁring strength wi and the Zi is used to calculate the output level zi of each rule.
The Defuzziﬁcation (DE) block is a process to calculate the ﬁnal output of system based on the weighted average of all rule outputs.
The processing diagram of the FLP is described as Figure 8. More detail about the design of the FLP has been presented in [12].
an output based on Sugeno model. The FLP 3.4.3. Fuzziﬁcation
is implemented by three blocks as depicted in Figure 7.
The Fuzziﬁcation (FZ) block is composed of two sub-blocks: input MSF1 and input MSF2. Each sub-block is a process to calculate the degree of each input (input 1 and input 2) based on the membership functions.
To simplify the explanation of MSFs mathematical formulation, and without loss of generality, let us consider only triangular/trapezoidal MSF.
A trapezoidal MSF is described by a set of parameters (point 1, b, c, point 2) as in Figure 9. The triangle MSF is the simpliﬁcation of trapezoidal MSF when the parameters point 2 and b are the same.
The Fuzzy Engine (FE) block includes To describe the triangle MSF easily, the set two sub-blocks: the AND-rule is used for ofparametersbecomes(point 1,slope 1,point 2,
H.P. Phan, X.T. Tran / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 31, No. 2 (2015) 56–65 61
parameters are described in Figure 10. The maximum value of the membership function vhigh is 0xC0, corresponding to the maximum value of trac is 192Mﬂits=s. This value is selected in accordance with the maximum communication speed of a router has been